Lead, coach, and develop a team of supply planners Meet KPI for SCM (on time delivery, revenue attainment, excess & obsolete, etc.) Collaborate with other functions to communicate priorities, strategies, and close operational gaps Accountable to position supply required to meet new product milestones & demand ramp, while minimizing supply risk Lead resolution of issues to

Driving technical innovation to improve AMD's capabilities across validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross functional technical initiatives Debugging issues found during the process, bring up, validation, and production phases of SOC programs Working with multiple teams, and trackin

Drive AMD's strategy to compete in the python based GPU accelerated AI market. Break down complex AI workloads, delve into lower level library dependencies, and devise strategic optimization plans to enhance performance and efficiency. Form and lead strategic partnerships to enhance ROCm's presence in the python AI marketspace. Collaborate closely with Engineering and Sol

Train and finetune LLMs/LMMs. Improve on the state of the art LLMs/LMMs.. Accelerate the training and inference speed of LLMs/LMMs. Research novel ML techniques and model architectures. Influence the direction of AMD AI platform. Publish your work at top tier venues. PREFERRED EXPERIENCE Experience in developing and debugging in Python. Experience in ML frameworks such as

Lead hybrid project management teams focused on security improvements for the Instinct GPU line Analyze incoming security vulnerabilities to assess GPU focused product impact and software based mitigation options Engage technical leadership frequently to complete phase gate process for vulnerability assessment and response to external customers/general public Manage Jira

Define verification plan, and provide technical direction to execution teams Comprehend AMS, Firmware and design spec. Work with other functional leads to come up with a DV plan and execute the plan. Create UVM/SystemVerilog based testbenches and tests. Make sure that design is bug free. Lead Formal verification. Support Post Si teams for Product Performance, Power and fu

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL an

Manage a team of RTL engineers Technical leadership within an RTL team, and across other core teams Identify bottlenecks and propose new features to improve Floating Point performance. Work with performance modeling team to model and study new features. Identify power and area optimizations, supporting multiple design variants Implement new features in RTL, working with p

This individual will be responsible for participating and driving large design blocks from early design stage to tapeout. Work responsibilities include synthesizing extremely high speed designs, following through with Place and Route and analyzing design results, and making changes to the RTL code as needed. Work involves daily interaction with other physical designers as

Main focus Develop technical relationships with target customer base Win new AMD server opportunities with target customers Support customer engineering teams throughout server development process Drive customer feedback into AMD sales, business unit and engineering teams More day to day will include Provide technical guidance to sales personnel and the customer in the ev

Develop new flow features around new EDA tools and tool capabilities Conduct evaluations of tool quality, tune the flow to get optimal results from existing tools and support the physical verification flow Deploy flows to design teams, work with design teams to help them take full advantage of the flow PREFERRED EXPERIENCE Expert knowledge of at least one EDA Physical ver

Should have Senior level architect experience. Strong background in I/O. Extensive experience in performance analysis. Architecture background of one or more non CPU System Components Industry experience in system performance modeling and/or workload characterization Background in System Architecture Research. Familiarity with classic Server NIC and disk I/O performance.

Excellent knowledge of C, C++, SystemVerilog, UVM object oriented design as well as scripting language. Experience in ground up development and verification using UVM/SystemVerilog with IP and Subsystem verification as main objective using VCS. Advanced testbench architecture, microarchitecture, development, and implementation experience, including co verification. In dep

Develop and drive design review processes of our customers base system implementations and flag areas that could be modified to improve quality, performance, security, or other areas key for their competitiveness. Provide architectural guidance and support to our SDE team and customers as we help them adapt their HPC and AI servers developed with our competition's GPU sol

Perform data mining and statistical data analysis on wafer sort and final test parametrics to support initial product assessment Work closely with Tools Development engineers to feedback binning, yield and parametric results to enhance various Tools' capabilities and functions Develop methodologies to automate analytical tasks using scripting languages Qualifications BS o